Structurally ternary substrate · standard binary CMOS
A third category of computing — ternary all the way down, printed on the same binary CMOS your foundry already runs. 5× more efficient AI today, on a path to the 12× frontier.
The frontier · Efficiency stack
There's no single trick. Three independent advantages compound: a structurally ternary substrate, ternary models, and an integrated SoC. Drag the workload from balanced to AI-heavy and watch the envelope move — every layer is graded by evidence.
Composite AI performance‑per‑watt versus an ARM Neoverse N3 reference — folded honestly from three measured & published layers.
We fold conservatively — the composite is deliberately smaller than the naïve product of the three layers. Every figure traces to on-disk silicon-grade evidence.
Live silicon · ternary in motion
Real time, in 3D: weight trits stream into the compute core — +1 passes straight through, −1 flips for free, 0 is skipped entirely — and the result accumulates. Drag to orbit, tap a floating trit, or pulse a batch.
Demo 1 · Throughput & energy
Same prompt. Same hardware budget. Two architectures. The ratios are what matter — T3ISC delivers the same answer faster while using a fraction of the energy.
Ratios derived from measured architectural metrics (energy/MAC, whole-SoC energy, area). Absolute throughput depends on process node, tile size, and workload — see the headline-numbers panel for the underlying figures.
Demo 2 · Ternary Data Flow
Each system has a source chamber, a pipe, and a compute chamber. Binary needs the full pipe to deliver every bit. Ternary moves only the trits that matter — same result, 8× less data through the pipe.
Why this matters: Ternary software on binary silicon wastes the 8× bandwidth saving. Binary software on ternary silicon blocks the pipeline at the boundary. Only with native ternary silicon + native ternary software do you capture the full advantage end-to-end.
Demo 3 · At scale
Pick a workload. See how many conventional racks it would take versus how many T3ISC racks deliver the same throughput.
Rack counts are illustrative ratios derived from measured architectural metrics (5.0× whole-SoC energy, 5.35× area). Real deployments depend on process node, memory tier, and workload mix.
About
T3ISC has built ternary computing implemented in standard binary CMOS transistors. Standard fabs. Standard process nodes. Structurally ternary substrate — the architecture is ternary all the way down, but every transistor underneath is the same one your foundry already manufactures by the billions. Printable on any 180 nm-to-3 nm CMOS line today — no specialised process, no exotic devices and no special ternary transistors.
The two existing approaches both fail. Specialised hardware ternary (FeFET, MRAM, multi-Vth) requires non-standard fabs and decade-long device-physics work. Software ternary (BitNet, PrismML) treats ternary as an algorithm only — the model is ternary, the silicon underneath is still binary FP16, and no hardware value is captured.
T3ISC is the third category. Patents filed. Verified on three SIMT platforms (NVIDIA CUDA, Apple Silicon Metal, Linux ARM). 100% simulation-evidence-complete across 16 architectural components:
We are looking for Partners and investors to help us licence this architecture and to bring the future forwards.
History
Ternary computing has a 68-year academic history. T3ISC is the first practical commercialisation on standard binary CMOS.
The future
From simulation to silicon to scale.
Team
Lead engineer and inventor. Architecture, ISA design, full-stack verification. Inventor and patent filer for the T3ISC substrate.
We are hiring senior silicon engineers, ML systems engineers, and full-stack T3ISC backend developers. [email protected]
Engage
Email: [email protected]
Media
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